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| STV160NF03LA N-CHANNEL 30V - 0.0021 - 160A PowerSO-10 STripFETTM POWER MOSFET TYPE STV160NF03LA s s s s s s s VDSS 30 V RDS(on) < 0.003 ID 160 A TYPICAL RDS(on) = 0.0021 LOW THRESHOLD DRIVE ULTRA LOW ON-RESISTANCE ULTRA FAST SWITCHING 100% AVALANCHE TESTED VERY LOW GATE CHARGE LOW PROFILE, VERY LOW PARASITIC INDUCTANCE PowerSO-10 PACKAGE 10 1 PowerSO-10 INTERNAL SCHEMATIC DIAGRAM DESCRIPTION The STV160NF03LA represents the second generation of Application Specific STMicroelectronics well established STripFETTM process based on a very unique strip layout design. The resulting MOSFET shows unrivalled high packing density with ultra low on-resistance and superior switching charactestics. Process simplification also translates into improved manufacturing reproducibility. This device is particularly suitable for high current, low voltage switching application where efficiency is crucial APPLICATIONS s BUCK CONVERTERS IN HIGH PERFORMANCE TELECOM AND VRMs DCDC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(**) ID IDM (q) PTOT EAS (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature CONNECTION DIAGRAM (TOP VIEW) Value 30 30 15 160 113 640 210 1.4 330 -65 to 175 175 Unit V V V A A A W W/C mJ C C (q) Pulse width limited by safe operating area Note: Marking will be STV160NF03AL December 2000 (1) VDD = 35V, ID = 45A, RG = 22 , L = 330H, Starting Tj=25C (**)Limited only maximum junction temperature allowed by PowerSO-10 1/8 STV160NF03LA THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.71 50 300 C/W C/W C ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 15 V Min. 30 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10 V, ID = 80 A VGS = 10 V, ID = 45 A VGS = 8 V, ID = 80 A VGS = 5 V, ID = 40 A VGS = 10 V, ID=80 A;Tj = 175 C VGS = 8 V, ID=80 A; Tj = 175 C VGS = 5 V, ID=40 A; Tj = 175 C VDS > ID(on) x RDS(on)max, VGS = 10V 160 Min. 1 2.1 2.05 2.2 4.2 3 3 4 7 6.6 8.8 15.4 Typ. Max. Unit V m m m m m m m A ID(on) On State Drain Current DYNAMIC Symbol gfs (1) Rg Ciss Coss Crss Ciss Coss Crss LS Parameter Forward Transconductance Gate resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Source Inductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 80 A VDS = 0 V, f = 1 MHz, VGS = 0 VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 210 1.1 5350 1700 300 8200 12400 5200 3 Max. Unit S pF pF pF pF pF pF nH VDS = 0 V, f = 1 MHz, VGS = 0 From the Lead End (6mm from Package Body) to the Die Center LD Internal Drain Inductance Not Available on Surface Mounting Package 2/8 STV160NF03LA ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15 V, ID = 80 A RG = 4.7 VGS = 10V (see test circuit, Figure 3) VDD = 24 V, ID = 160 A, VGS = 10 V Min. Typ. 30 380 123 21 40 160 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf td(off) tr(Voff) tf tc Parameter Turn-off-Delay Time Fall Time Turn-off Delay Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 15 V, ID = 80 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 5) Vclamp = 24 V, ID = 40 A RG = 4.7, VGS = 10V Min. Typ. 100 150 95 35 75 110 Max. Unit ns ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (1) VSD (2) trr Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time ISD = 160 A, VGS = 0 ISD = 160A, di/dt = 100A/s, VDD = 15V, Tj = 25C (see test circuit, Figure 5) 80 ns 180 4.5 nC A Test Conditions Min. Typ. Max. 160 640 1.5 Unit A A V Qrr IRRM Reverse Recovery Charge Reverse Recovery Current Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STV160NF03LA Output Characteristics Tranfer Characteristics Tranconductance Static Drain-Source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STV160NF03LA Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Basic Schematic For Motherboard VRM Whith Synchronous Rectification Basic Schematic Mosfets Switch Used In Secondary Side Of a Froward Convert 5/8 STV160NF03LA Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STV160NF03LA PowerSO-10 MECHANICAL DATA DIM. MIN. A A1 B C D D1 e E E1 E2 E3 E4 F h H L q 0o 13.80 1.20 1.70 8o 9.30 7.20 7.20 6.10 5.90 1.25 0.50 14.40 1.80 0.543 0.047 0.067 3.35 0.00 0.40 0.35 9.40 7.40 1.27 9.50 7.40 7.60 6.35 6.10 1.35 0.366 0.283 0.283 0.240 0.232 0.049 0.002 0.567 0.071 mm TYP. MAX. 3.65 0.10 0.60 0.55 9.60 7.60 MIN. 0.132 0.000 0.016 0.013 0.370 0.291 0.050 0.374 0.291 0.300 0.250 0.240 0.053 inch TYP. MAX. 0.144 0.004 0.024 0.022 0.378 0.300 B 0.10 A B 10 6 = H E = E2 E3 E1 = = 1 5 = SEATING PLANE DETAIL "A" Q e 0.25 M B A C D h = A F A1 = D1 = = SEATING PLANE = = = = = = E4 = A1 L DETAIL "A" 0068039-C 7/8 STV160NF03LA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 8/8 |
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